View DAC9881_9066612.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 features description applications DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 18-bit, single-channel, low-noise, voltage-output digital-to-analog converter 234 18-bit monotonic over temperature range the DAC9881 is an 18-bit, single-channel, voltage-output digital-to-analog converter (dac). it relative accuracy: 2lsb max features 18-bit monotonicity, excellent linearity, very low-noise: 24nv/ hz low-noise, and fast settling time. the on-chip fast settling: 5 m s precision output amplifier allows rail-to-rail output on-chip output buffer amplifier with swing to be achieved over the full supply range of 2.7v to 5.5v. rail-to-rail operation single power supply: +2.7v to +5.5v the device supports a standard spi serial interface capable of operating with input data clock frequencies dac loading control up to 50mhz. the DAC9881 requires an external selectable power-on reset to zero-scale or reference voltage to set the output range of the dac midscale channel. a programmable power-on reset circuit is power-down mode also incorporated into the device to ensure that the dac output powers up at zero-scale or midscale, and unipolar straight binary or remains there until a valid write command. twos complement input mode additionally, the DAC9881 has the capability to fast spi? interface with schmitt-triggered function in either unipolar straight binary or twos inputs: up to 50mhz, 1.8v/3v/5v logic complement mode. the DAC9881 provides small package: qfn-24, 4mm 4mm low-power operation. to further save energy, power-down mode can be achieved by accessing the pdn pin, thereby reducing the current consumption to automatic test equipment 25 m a at 5v. power consumption is 4mw at 5v, reducing to 125 m w in power-down mode. precision instrumentation industrial control the DAC9881 is available in a 4mm 4mm qfn-24 data acquisition systems package with a specified temperature range of ? 40 c to +105 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 spi, qspi are trademarks of motorola, inc. 3 microwire is a trademark of national semiconductor. 4 all other trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. DAC9881 r fb (1) control logic dgnd iov dd agnd av dd v -s refh v -f refh rst rstsel usb/btc gain sdi cs sclk spi interface shift register input register dac latch ldac v -s refl v -f refl resistornetwork dac note: (1) r = 5k for gain = 1, w fb r = 10k for gain = 2. w fb DAC9881 serial out control sdosel sdo power-on reset pdnv out r fb
absolute maximum ratings (1) DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) relative differential specified accuracy nonlinearity package- package temperature package product (lsb) (lsb) lead designator range marking DAC9881s 3 ? 1/+2 qfn-24 rge ? 40 c to +105 c DAC9881 DAC9881sb 2 1 qfn-24 rge ? 40 c to +105 c DAC9881b (1) for the most current package and ordering information, see the package option addendum at the end of this data sheet, or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted). parameter DAC9881 unit av dd to agnd ? 0.3 to 6 v iov dd to dgnd ? 0.3 to 6 v digital input voltage to dgnd ? 0.3 to iov dd + 0.3 v v out to agnd ? 0.3 to av dd + 0.3 v operating temperature range ? 40 to +105 c storage temperature range ? 65 to +150 c maximum junction temperature (t j max) +150 c thermal impedance ( q ja ) 46 c/w human body model (hbm) 3000 v esd ratings charged device model (cdm) 1000 v (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. 2 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881
electrical characteristics: av dd = 5v DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 all specifications at t a = t min to t max , av dd = +4.75v to +5.5v, iov dd = +1.8v to +5.5v, v refh = 5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. DAC9881 parameter conditions min typ max unit accuracy (1) measured by line DAC9881s 2 3 lsb passing through integral linearity error codes 2048 and DAC9881sb 1 2 lsb 260096 measured by line DAC9881s ? 1 0.75 +2 lsb passing through differential linearity error codes 2048 and DAC9881sb 0.5 1 lsb 260096 monotonicity 18 bits t a = +25 c, code = 2048 16 lsb zero-scale error t min to t max , code = 2048 32 lsb zero-scale drift (2) code = 2048 0.25 0.8 ppm/ c of fsr t a = +25 c, measured by line passing through codes 2048 gain error 16 32 lsb and 260096 gain temperature drift (2) measured by line passing through codes 2048 and 260096 0.25 0.4 ppm/ c psrr (2) v out = full-scale, av dd = +5v 10% 32 lsb/v analog output (2) voltage output (3) 0 av dd v device operating for 500 hours at +25 c 0.1 ppm of fsr output voltage drift vs time device operating for 1000 hours at +25 c 0.2 ppm of fsr output current (4) 2.5 ma maximum load capacitance 200 pf short-circuit current +31/ ? 50 ma reference input (2) v refh input voltage range av dd = +5.5v 1.25 5.0 av dd v v refh input capacitance 5 pf v refh input impedance 4.5 k ? v refl input voltage range ? 0.2 0 +0.2 v v refl input capacitance 4.5 pf v refl input impedance 5 k ? dynamic performance (2) to 0.003% fs, r l = 10k ? , c l = 50pf, code 04000h to settling time 5 m s 3c000h slew rate from 10% to 90% of 0v to +5v 2.5 v/ m s v refh = 5v, gain = 1x mode 37 nv-s v refh = 2.5v, gain = 1x mode 18 nv-s code = 1ffffh to code change glitch v refh = 1.25v, gain = 1x mode 9 nv-s 20000h to 1ffffh v refh = 2.5v, gain = 2x mode 21 nv-s v refh = 1.25v, gain = 2x mode 10 nv-s digital feedthrough cs = high, f sclk = 1khz 1 nv-s gain = 1 24 30 nv/ hz f = 1khz to 100khz, output noise voltage density full-scale output gain = 2 40 48 nv/ hz output noise voltage f = 0.1hz to 10hz, full-scale output 2 m v pp (1) dac output range is 0v to +5v. 1lsb = 19 m v. (2) ensured by design. not production tested. (3) the output from the v out pin = [(v refh ? v refl )/262144] code buffer gain + v refl . the maximum range of v out is 0v to av dd . the full-scale of the output must be less than av dd ; otherwise, output saturation occurs. (4) refer to figure 26 , figure 27 , and figure 28 for details. copyright ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): DAC9881
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com electrical characteristics: av dd = 5v (continued) all specifications at t a = t min to t max , av dd = +4.75v to +5.5v, iov dd = +1.8v to +5.5v, v refh = 5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. DAC9881 parameter conditions min typ max unit digital inputs (5) iov dd = 4.5v to 5.5v 3.8 iov dd + 0.3 v high-level input voltage, v ih iov dd = 2.7v to 3.3v 2.1 iov dd + 0.3 v iov dd = 1.7v to 2.0v 1.5 iov dd + 0.3 v iov dd = 4.5v to 5.5v ? 0.3 0.8 v low-level input voltage, v il iov dd = 2.7v to 3.3v ? 0.3 0.6 v iov dd = 1.7v to 2.0v ? 0.3 0.3 v digital input current (i in ) 1 10 m a digital input capacitance 5 pf digital output (5) iov dd = 2.7v to 5.5v, i oh = ? 1ma iov dd ? 0.2 v high-level output voltage, v oh iov dd = 1.7v to 2.0v, i oh = ? 500 m a iov dd ? 0.2 v iov dd = 2.7v to 5.5v, i ol = 1ma 0.2 v low-level output voltage, v ol iov dd = 1.7 to 2.0v, i ol = 500 m a 0.2 v power supply av dd +4.75 +5.0 +5.5 v iov dd +1.7 av dd v ai dd v ih = iov dd , v il = dgnd 0.85 1.5 ma ioi dd v ih = iov dd , v il = dgnd 1 10 m a ai dd power-down pdn pin = iov dd 25 50 m a power dissipation av dd = 5.0v 4.3 7.5 mw temperature range specified performance ? 40 +105 c (5) ensured by design. not production tested. 4 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881
electrical characteristics: av dd = 2.7v DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 all specifications at t a = t min to t max , av dd = +2.7v to +3.3v, iov dd = +1.8v to av dd , v refh = 2.5v, v refl = 0v and gain = 1x mode, unless otherwise noted. DAC9881 parameter conditions min typ max unit accuracy (1) measured by line DAC9881s 2.5 3.5 lsb passing through integral linearity error codes 2048 and DAC9881sb 2 3 lsb 262143 measured by line DAC9881s 1 2 lsb passing through differential linearity error codes 2048 and DAC9881sb 0.75 1.5 lsb 262143 t a = +25 c, code = 2048 32 lsb zero-scale error t min to t max , code = 2048 64 lsb zero-scale drift (2) code = 2048 0.5 1.6 ppm/ c of fsr t a = +25 c, measured by line passing through codes 2048 gain error 32 64 lsb and 262143 gain temperature drift (2) measured by line passing through codes 2048 and 262143 0.5 0.8 ppm/ c psrr (2) v out = full-scale, av dd = +3v 10% 64 lsb/v analog output (2) voltage output (3) 0 av dd v device operating for 500 hours at +25 c 0.2 ppm of fsr output voltage drift vs time device operating for 1000 hours at +25 c 0.4 ppm of fsr output current (4) 2.5 ma maximum load capacitance 200 pf short-circuit current +31/ ? 50 ma reference input (2) v refh input voltage range av dd = +3v 1.25 2.5 av dd v v refh input capacitance 5 pf v refh input impedance 4.5 k ? v refl input voltage range ? 0.2 0 +0.2 v v refl input capacitance 4.5 pf v refl input impedance 5 k ? dynamic performance (2) to 0.003% fs, r l = 10k ? , c l = 50pf, code 04000h to settling time 5 m s 3c000h slew rate from 10% to 90% of 0v to +2.5v 2.5 v/ m s v refh = 2.5v, gain = 1x mode 18 nv-s code = 1ffffh to code change glitch v refh = 1.25v, gain = 1x mode 9 nv-s 20000h to 1ffffh v refh = 1.25v, gain = 2x mode 10 nv-s digital feedthrough cs = high, f sclk = 1khz 1 nv-s gain = 1 24 30 nv/ hz f = 1khz to 100khz, output noise voltage density full-scale output gain = 2 40 48 nv/ hz output noise voltage f = 0.1hz to 10hz, full-scale output 2 m v pp (1) dac output range is 0v to +2.5v. 1lsb = 9.5 m v. (2) ensured by design. not production tested. (3) the output from the v out pin = [(v refh ? v refl )/262144] code buffer gain + v refl . the maximum range of v out is 0v to av dd . the full-scale of the output must be less than av dd ; otherwise, output saturation occurs. (4) refer to figure 55 , figure 56 , and figure 57 for details. copyright ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): DAC9881
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com electrical characteristics: av dd = 2.7v (continued) all specifications at t a = t min to t max , av dd = +2.7v to +3.3v, iov dd = +1.8v to av dd , v refh = 2.5v, v refl = 0v and gain = 1x mode, unless otherwise noted. DAC9881 parameter conditions min typ max unit digital inputs (5) iov dd = 2.7v to 3.3v 2.1 iov dd + 0.3 v high-level input voltage, v ih iov dd = 1.7v to 2.0v 1.5 iov dd + 0.3 v iov dd = 2.7v to 3.3v ? 0.3 0.6 v low-level input voltage, v il iov dd = 1.7v to 2.0v ? 0.3 0.3 v digital input current (i in ) 1 10 m a digital input capacitance 5 pf digital output (5) iov dd = 2.7v to 3.3v, i oh = ? 1ma iov dd ? 0.2 v high-level output voltage, v oh iov dd = 1.7v to 2.0v, i oh = ? 500 m a iov dd ? 0.2 v iov dd = 2.7v to 3.3v, i ol = 1ma 0.2 v low-level output voltage, v ol iov dd = 1.7 to 2.0v, i ol = 500 m a 0.2 v power supply av dd +2.7 +3.0 +3.3 v iov dd +1.7 av dd v ai dd v ih = iov dd , v il = dgnd 0.75 1.2 ma ioi dd v ih = iov dd , v il = dgnd 1 10 m a ai dd power-down pdn pin = iov dd 25 50 m a power dissipation av dd = 3.0v 2.3 3.6 mw temperature range specified performance ? 40 +105 c (5) ensured by design. not production tested. 6 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881
pin configuration DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 rge package (1) qfn-24 (top view) (1) the thermal pad is internally connected to the substrate. this pad can be connected to the analog ground or left floating. keep the thermal pad separate from the digital ground, if possible. terminal functions terminal no. name i/o description 1 sclk i spi bus serial clock input 2 sdi i spi bus serial data input load dac latch control input (active low). when ldac is low, the dac latch is transparent, and the contents of the input 3 ldac i register are transferred to the dac latch. the dac output changes to the corresponding level simultaneously when the dac latch is updated. it is recommended to connect this pin to iov dd through a pull-up resistor. 4 agnd i analog ground 5 av dd i analog power supply 6 v refl -s i reference low input sense 7 v refh -s i reference high input sense 8 v out o output of output buffer 9 r fb i feedback resistor connected to the inverting input of the output buffer. 10 v refl -f i reference low input force 11 v refh -f i reference high input force 12 nc ? do not connect. 13 nc ? do not connect. selects the value of the output from the v out pin after power-on or hardware reset. if rstsel = iov dd , then register data 14 rstsel i = 20000h. if rstsel = dgnd, then register data = 00000h. 15 gain i buffer gain setting. gain = 1 when the pin is connected to dgnd; gain = 2 when the pin is connected to iov dd . input data format selection. input data are straight binary format when the pin is connected to iov dd , and in twos 16 usb/ btc i complement format when the pin is connected to dgnd. 17 rst i reset input (active low). logic low on this pin causes the device to perform a reset. power-down input (active high). logic high on this pin forces the device into power-down status. in power-down, the v out 18 pdn i pin connects to agnd through a 10k ? resistor. spi bus chip select input (active low). data bits are not clocked into the serial shift register unless cs is low. when cs is 19 cs i high, sdo is in a high-impedance state. it is recommended to connect this pin to iov dd through a pull-up resistor. spi serial data output selection. when sdosel is tied to iov dd , the contents of the existing input register are shifted out 20 sdosel i from the sdo pin; this is stand-alone mode. when sdosel is tied to dgnd, the contents in the spi input shift register are shifted out from the sdo pin; this is daisy-chain mode for daisy-chained communication. 21 av dd i analog power supply. must be connected to pin 5. 22 dgnd i digital ground 23 sdo o spi bus serial data output. refer to the timing diagrams for further detail. 24 iov dd i interface power. connect to +1.8v for 1.8v logic, +3v for 3v logic, and to +5v for 5v logic. copyright ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): DAC9881 sclk sdi ldac agnd av dd v -s refl (thermal pad) (1) pdnrst usb/btc gainrstsel nc 12 3 4 5 6 1817 16 15 14 13 DAC9881 iov dd sdo dgnd av dd sdosel cs 24 23 22 21 20 19 v -s ref h v out r fb v -f refl v -f ref h nc 7 8 9 10 11 12
timing diagrams DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com figure 1. timing diagram for standalone operation without sdo 8 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 cs case 1: standalone operation without sdo, tied low. ldac case 2: standalone operation without sdo, active. ldac sclk sdi ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 input register and dac latch updated low bit 23 (n) bit 22 (n) bit 1 (n) bit 0 (n) cs sclk sdi ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 input register updated high = dont care bit 23 = msbbit 0 = lsb bit 23 (n) bit 22 (n) bit 1 (n) bit 0 (n) dac latch updated t 14 t 15
timing characteristics for figure 1 (1) (2) (3) DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 at ? 40 c to +105 c, unless otherwise noted. parameter conditions min max unit 2.7 av dd < 3.6v, 2.7 iov dd av dd 40 mhz f sclk maximum clock frequency 3.6 av dd 5.5v, 2.7 iov dd av dd 50 mhz 2.7 av dd < 3.6v, 2.7 iov dd av dd 50 ns t 1 minumum cs high time 3.6 av dd 5.5v, 2.7 iov dd av dd 30 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from cs falling edge to sclk rising t 2 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 8 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 0 ns delay from sclk falling edge to cs falling t 3 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 0 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns t 4 sclk low time 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 15 ns t 5 sclk high time 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 25 ns t 6 sclk cycle time 3.6 av dd 5.5v, 2.7 iov dd av dd 20 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from sclk rising edge to cs rising t 7 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 8 ns t 8 input data setup time 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 5 ns t 9 input data hold time 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from cs rising edge to ldac falling t 14 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 15 ns t 15 ldac pulse width 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns (1) all input signals are specified with t r = t f = 2ns (10% to 90% of iov dd ) and timed from a voltage level of iov dd /2. (2) ensured by design. not production tested. (3) sample tested during the initial release and after any redesign or process changes that may affect these parameters. copyright ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): DAC9881
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com figure 2. timing diagram for standalone operation with sdo 10 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 cs case 1: standalone operation with output from sdo, tied low. ldac case 2: standalone , active. operation with output from sdo ldac sclk sdi sdo ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 input register and dac latch updated high-z low high-z bit 23 (n 1) - from input reg. bit 22 (n 1) - from input reg. bit 1 (n 1) - from input reg. bit 0 (n 1) - from input reg. bit 23 (n) bit 22 (n) bit 1 (n) bit 0 (n) t 11 t 13 t 12 t 10 cs sclk sdi sdo ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 input register updated high-z high high-z = dont care bit 23 = msbbit 0 = lsb bit 23 (n 1) - from input reg. bit 22 (n 1) - from input reg. bit 1 (n 1) - from input reg. bit 0 (n 1) - from input reg. bit 23 (n) bit 22 (n) bit 1 (n) bit 0 (n) t 11 t 13 t 12 dac latch updated t 10 t 14 t 15
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 figure 3. timing diagram for daisy chain mode, two cascaded devices copyright ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): DAC9881 cs case 1: daisy chain, tied low. ldac case 2: daisy chain, active. ldac sclk sdi sdo ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 input register and dac latch updated high-z low high-z bit 23 (n) (1) bit 0 (n) bit 23 (n) bit 22 (n) bit 23 (n + 1) bit 0 (n + 1) bit 0 (n) t 11 t 13 t 12 t 10 = dont care bit 23 = msbbit 0 = lsb cs sclk sdi sdo ldac t 9 t 8 t 4 t 5 t 6 t 3 t 1 t 2 t 7 high-z high-z bit 23 (n) (1) bit 0 (n) bit 23 (n) bit 22 (n) bit 23 (n + 1) bit 0 (n + 1) bit 0 (n) t 11 t 13 t 12 t 10 input register updated high dac latch updated t 14 t 15 note: (1) sdo data delayed from sdi by 24 clock cycles.
timing characteristics for figure 2 and figure 3 (1) (2) (3) DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com at ? 40 c to +105 c, unless otherwise noted. parameter conditions min max unit 2.7 av dd < 3.6v, 2.7 iov dd av dd 20 mhz f sclk maximum clock frequency 3.6 av dd 5.5v, 2.7 iov dd av dd 25 mhz 2.7 av dd < 3.6v, 2.7 iov dd av dd 50 ns t 1 minumum cs high time 3.6 av dd 5.5v, 2.7 iov dd av dd 30 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from cs falling edge to sclk rising t 2 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 8 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 0 ns delay from sclk falling edge to cs falling t 3 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 0 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 25 ns t 4 sclk low time 3.6 av dd 5.5v, 2.7 iov dd av dd 20 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 25 ns t 5 sclk high time 3.6 av dd 5.5v, 2.7 iov dd av dd 20 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 50 ns t 6 sclk cycle time 3.6 av dd 5.5v, 2.7 iov dd av dd 40 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from sclk rising edge to cs rising t 7 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 5 ns t 8 input data setup time 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 5 ns t 9 input data hold time 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 15 ns t 10 delay from cs falling edge to sdo valid 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 20 ns t 11 delay from sclk falling edge to sdo valid 3.6 av dd 5.5v, 2.7 iov dd av dd 15 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd t 5 ns t 12 sdo data hold from sclk rising edge 3.6 av dd 5.5v, 2.7 iov dd av dd t 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 8 ns t 13 delay from cs rising edge to sdo high-z 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 10 ns delay from cs rising edge to ldac falling t 14 edge 3.6 av dd 5.5v, 2.7 iov dd av dd 5 ns 2.7 av dd < 3.6v, 2.7 iov dd av dd 15 ns t 15 ldac pulse width 3.6 av dd 5.5v, 2.7 iov dd av dd 10 ns (1) all input signals are specified with t r = t f = 2ns (10% to 90% of iov dd ) and timed from a voltage level of iov dd /2. (2) ensured by design. not production tested. (3) sample tested during the initial release and after any redesign or process changes that may affect these parameters. 12 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881
typical characteristics: av dd = +5v DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. linearity error differential linearity error vs digital input code vs digital input code figure 4. figure 5. linearity error differential linearity error vs digital input code vs digital input code figure 6. figure 7. linearity error differential lineary error vs digital input code vs digital input code figure 8. figure 9. copyright ? 2008, texas instruments incorporated submit documentation feedback 13 product folder link(s): DAC9881 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t = 40 - a c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) t = 40 - a c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t a = +25 c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) t c a = +25 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) t a = +105 c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t a = +105 c
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. linearity error differential linearity error vs temperature vs temperature figure 10. figure 11. linearity error differential linearity error vs temperature (gain = 2x mode) vs temperature (gain = 2x mode) figure 12. figure 13. linearity error differential linearity error vs supply voltage vs supply voltage figure 14. figure 15. 14 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 - 40 - 20 0 20 40 60 80 100 120 temperature ( c) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) v = 2.5v v = 0v refh refl inl min inl max - 40 - 20 0 20 40 60 80 100 120 temperature ( c) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) dnl min dnl max v = 2.5v v = 0v refh refl 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltage (v) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) inl max inl min v = 2.5v v = 0v refh refl 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 supply voltage (v) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) dnl max dnl min v = 2.5v v = 0v refh refl - 40 - 20 0 20 40 60 80 100 120 temperature ( c) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) inl min inl max - 40 - 20 0 20 40 60 80 100 120 temperature ( c) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) dnl min dnl max
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. linearity error differential linearity error vs reference voltage vs reference voltage figure 16. figure 17. full-scale and zero-scale error full-scale and zero-scale error vs temperature vs temperature (gain = 2x mode) figure 18. figure 19. av dd supply current av dd supply current vs digital input code vs digital input code (gain = 2x mode) figure 20. figure 21. copyright ? 2008, texas instruments incorporated submit documentation feedback 15 product folder link(s): DAC9881 - 55 - 35 - 15 125 5 25 45 65 85 105 temperature ( c) 1.00.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 full-scale and zero-scale error (mv) full-scale error zero-scale error - 55 - 35 - 15 125 5 25 45 65 85 105 temperature ( c) 1.00.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 full-scale and zero-scale error (mv) full-scale error zero-scale error v = 2.5v v = 0v refh refl 0 65536 131072 196608 262144 digital input code 11001000 900800 700 600 500 400 300 200 a supply current ( a) m v dd av = 2.7v dd v = 2.7v refh v = 0v refl av = 2.7v dd v = 2.5v refh v = 0v refl av = 5.0v dd v = 2.5v refh v = 0v refl av = 5.0v dd v = 5.0v refh v = 0v refl 0 65536 131072 196608 262144 digital input code 1000 900800 700 600 500 400 300 200 100 0 av supply current ( a) m dd av = 2.7v dd v = 1.25v refh v = 0v refl av = 5.0v dd v = 2.5v refh v = 0v refl av = 2.7v dd v = 1.25v refh v = 0v refl 0 1.0 2.0 3.0 4.0 5.0 6.0 reference voltage (v) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 inl error (lsb) inl max inl min 0 1.0 2.0 3.0 4.0 5.0 6.0 reference voltage (v) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) dnl max dnl min
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. av dd supply current av dd power-down current vs temperature vs temperature figure 22. figure 23. reference current reference current vs digital input code vs digital input code (gain = 2x mode) figure 24. figure 25. output voltage output voltage vs drive current capability vs drive current capability (operation near av dd rail) figure 26. figure 27. 16 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 0 1 2 3 4 5 i (ma) source 5.004.95 4.90 4.85 4.80 4.75 output voltage (v) dac loaded with 3e000h dac loaded with 3f800h dac loaded with 3f000h dac loaded with 3ffffh 0 3 6 9 12 15 i (ma) (source/sink) 5.04.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 output voltage (v) dac loaded with 3ffffh dac loaded with 00000h - 55 - 35 - 15 125 5 25 45 65 85 105 temperature ( c) 12001000 800600 400 200 0 av supply current ( a) m dd v = 5.0v refh v = 0v refl gain = 1x mode v refh = 2.5v v refl = 0v gain = 2x mode dac code set to 3f000h - 55 - 35 - 15 125 5 25 45 65 85 105 temperature ( c) 5040 30 20 10 0 a power-down current ( a) m v dd av = 5.0v dd av = 2.7v dd 0 262144 196608 131072 65536 digital input code 1.51.0 0.5 0 - 0.5 - 1.0 - 1.5 reference current (ma) v current refh v current refl 0 262144 196608 131072 65536 digital input code 1.51.0 0.5 0 - 0.5 - 1.0 - 1.5 reference current (ma) v current refh v = 2.5v refh v = 0v refl v current refl
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. output voltage vs drive current capability iov dd supply current (operation near agnd rail) vs logic input voltage figure 28. figure 29. large signal large signal settling time settling time figure 30. figure 31. large signal large signal settling time settling time figure 32. figure 33. copyright ? 2008, texas instruments incorporated submit documentation feedback 17 product folder link(s): DAC9881 time (2 s/div) m 2v/div 1mv/div 5v/div large- signal output ldac signal code change: 3ffffh to 00000h output loaded with 10k and w 50pf to agnd small-signal error time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output ldac signal code change: 04000h to 3c000h output loaded with 10k and w 50pf to agnd small-signal error time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output ldac signal code change: 3c000h to 04000h output loaded with 10k and w 50pf to agnd small-signal error 0 1 2 3 4 5 i (ma) sink 0.250.20 0.15 0.10 0.05 0 output voltage (v) dac loaded with 00800h dac loaded with 02000h dac loaded with 01000h dac loaded with 00000h 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 4.0 5.0 logic input voltage (v) 200180 160 140 120 100 8060 40 20 0 iov supply current ( a) m dd iov = 5v dd iov = 2.7v dd time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output ldac signal code change: 00000h to 3ffffh output loaded with 10k and w 50pf to agnd small-signal error
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. large signal large signal settling time (gain = 2x mode) settling time (gain = 2x mode) figure 34. figure 35. large signal large signal settling time (gain = 2x mode) settling time (gain = 2x mode) figure 36. figure 37. major carry glitch major carry glitch figure 38. figure 39. 18 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output ldac signal code change: 3c000h to 04000h output loaded with 10k and w 50pf to agnd small-signal error v = 2.5v refh time (2 m s/div) 100mv/div 5v/div v out signal ldac signal code change: 1ffffh to 20000h output loaded with 10k and w 50pf to agnd integrated glitch energy (38nv-s) gain = 1x modev refh = +5v time (2 m s/div) 100mv/div 5v/div v out signal ldac signal integrated glitch energy (28nv-s) gain = 1x modev refh = +5v code change: h to h 20000 1ffff output loaded with 10k and w 50pf to agnd time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output v = 2.5v refh ldac signal code change: 00000h to 3ffffh output loaded with 10k and w 50pf to agnd small-signal error time (2 s/div) m 2v/div 1mv/div 5v/div large- signal output ldac signal code change: 3ffffh to 00000h output loaded with 10k and w 50pf to agnd small-signal error v = 2.5v refh time (2 s/div) m 2v/div 1mv/div 5v/div large-signal output ldac signal code change: 04000h to 3c000h output loaded with 10k and w 50pf to agnd small-signal error v = 2.5v refh
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 typical characteristics: av dd = +5v (continued) at t a = +25 c, v refh = +5.0v, v refl = 0v, and gain = 1x mode, unless otherwise noted. major carry glitch major carry glitch figure 40. figure 41. output noise density low-frequency output noise vs frequency (0.1hz to 10hz) figure 42. figure 43. copyright ? 2008, texas instruments incorporated submit documentation feedback 19 product folder link(s): DAC9881 time (2 m s/div) 100mv/div 5v/div v out signal ldac signal integrated glitch energy (15nv-s) gain = 1x modev refh = +2.5v code change: 20000h to h 1ffff output loaded with 10k and w 50pf to agnd 2 v/div m time (1s/div) 1 10 100 1k 10k 100k frequency (hz) 180160 140 120 100 8060 40 20 0 output voltage noise density (nv/ ) ? hz gain = 1x mode gain = 2x mode dac code set to 20000h output unloaded time (2 s/div) m 100mv/div 5v/div v signal out ldac signal integrated glitch energy (17nv-s) gain = 1x modev refh = +2.5v code change: 1ffffh to 20000h output loaded with 10k and w 50pf to agnd
typical characteristics: av dd = +2.7v DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com at t a = +25 c, v refh = +2.5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. linearity error differential linearity error vs digital input code vs digital input code figure 44. figure 45. linearity error differential linearity error vs digital input code vs digital input code figure 46. figure 47. linearity error differential linearity error vs digital input code vs digital input code figure 48. figure 49. 20 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t a = +25 c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 3.02.0 1.0 0 - 1.0 - 2.0 - 3.0 inl error (lsb) t = 40 - a c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t a = 40 - c 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code t a = +105 c 3.02.0 1.0 0 - 1.0 - 2.0 - 3.0 inl error (lsb) 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) t = +105 c a 32768 0 262144 229376 196608 163840 131072 98304 65536 digital input code 3.02.0 1.0 0 - 1.0 - 2.0 - 3.0 inl error (lsb) t = +25 c a
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 typical characteristics: av dd = +2.7v (continued) at t a = +25 c, v refh = +2.5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. linearity error differential linearity error vs reference voltage vs reference voltage figure 50. figure 51. av dd supply current reference current vs temperature vs digital input code figure 52. figure 53. reference current output voltage vs digital input code (gain = 2x mode) vs drive current capability figure 54. figure 55. copyright ? 2008, texas instruments incorporated submit documentation feedback 21 product folder link(s): DAC9881 0 0.5 1.0 1.5 2.0 2.5 3.0 reference voltage (v) 4.03.0 2.0 1.0 0 - 1.0 - 2.0 - 3.0 - 4.0 inl error (lsb) inl max inl min 0 0.5 1.0 1.5 2.0 2.5 3.0 reference voltage (v) 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dnl error (lsb) dnl max dnl min - 55 - 35 - 15 125 5 25 45 65 85 105 temperature ( c) dac code set to 3ffffh 1000 900800 700 600 500 400 300 200 100 0 av supply current ( a) m dd v = 2.5v ref , gain = 1x mode v = 1.25v ref , gain = 2x mode 0 262144 196608 131072 65536 digital input code 1.000.75 0.50 0.25 0 - 0.25 - 0.50 - 0.75 - 1.00 reference current (ma) v current refh v = 2.5v refh v = 0v refl v current refl 0 262144 196608 131072 65536 digital input code 1.000.75 0.50 0.25 0 - 0.25 - 0.50 - 0.75 - 1.00 reference current (ma) v current refh v = 1.25v refh v = 0v refl v current refl 0 3 6 9 12 15 i (ma) (source/sink) 3.02.5 2.0 1.5 1.0 0.5 0 output voltage (v) dac loaded with 00000h dac loaded with 3ffffh, v = 2.5v refh dac loaded with 3ffffh, v = 2.7v refh
DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com typical characteristics: av dd = +2.7v (continued) at t a = +25 c, v refh = +2.5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. output voltage output voltage vs drive current capability vs drive current capability (operation near av dd rail) (operation near agnd rail) figure 56. figure 57. large signal large signal settling time settling time figure 58. figure 59. large signal large signal settling time settling time figure 60. figure 61. 22 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 time (2 s/div) m 1v/div 1mv/div 5v/div large-signal output ldac signal code change: 04000h to 3c000h output loaded with 10k and w 50pf to agnd small-signal error time (2 s/div) m 1v/div 1mv/div 5v/div large-signal output ldac signal code change: 3c000h to 04000h output loaded with 10k and w 50pf to agnd small-signal error 0 1 2 3 4 5 i (ma) source 2.702.65 2.60 2.55 2.50 2.45 2.40 output voltage (v) dac loaded with 3ffffh dac loadedwith 3f800h dac loadedwith 3f000h dac loadedwith 3e000h dac loaded with 3ffffh, v = 2.5v refh v , unless otherwise noted. refh = 2.7v 0 1 2 3 4 5 i (ma) sink 0.250.20 0.15 0.10 0.05 0 output voltage (v) dac loadedwith 00800h dac loadedwith 01000h dac loadedwith 02000h dac loaded with 00000h time (2 s/div) m 1v/div 1mv/div 5v/div large-signal output ldac signal code change: 00000h to 3ffffh output loaded with 10k and w 50pf to agnd small-signal error time (2 s/div) m 1v/div 1mv/div 5v/div large-signal output ldac signal code change: 3ffffh to 00000h output loaded with 10k and w 50pf to agnd small-signal error
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 typical characteristics: av dd = +2.7v (continued) at t a = +25 c, v refh = +2.5v, v refl = 0v, and gain = 1x mode, unless otherwise noted. major carry glitch major carry glitch figure 62. figure 63. copyright ? 2008, texas instruments incorporated submit documentation feedback 23 product folder link(s): DAC9881 time (2 m s/div) 100mv/div 5v/div v out signal ldac signal code change: 1ffffh to 20000h output loaded with 10k and w 50pf to agnd integrated glitch energy (16.5nv-s) gain = 1x modev refh = +2.5v time (2 s/div) m 100mv/div 5v/div v signal out ldac signal code change: 20000h to 1ffffh output loaded with 10k and w 50pf to agnd integrated glitch energy (17.5nv-s) gain = 1x modev refh = +2.5v
theory of operation general description DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com the DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (dac). the architecture is an r-2r ladder configuration with the four msbs segmented, followed by an operational amplifier that serves as a buffer, as shown in figure 64 . the on-chip output buffer allows rail-to-rail output swings while providing a low output impedance to drive loads. the DAC9881 operates from a single analog power supply that ranges from 2.7v to 5.5v, and typically consumes 850 m a when operating with a 5v supply. data are written to the device in a 24-bit word format, via an spi serial interface. to enable compatibility with 1.8v, 3v, or 5v logic families, an iov dd supply pin is provided. this pin allows the DAC9881 input and output logic to be powered from the same logic supply used to interface signals to and from the device. internal voltage translators are included in the DAC9881 to interface digital signals to the device core. see figure 65 for the basic configuration of the DAC9881. to ensure a known power-up state, the DAC9881 is designed with a power-on reset function. upon power-up, the DAC9881 is reset to either zero-scale or midscale depending on the state of the rstsel pin. a harrdware reset can be performed by using the rst and rstsel pins. figure 64. DAC9881 architecture 24 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 r 2r 2r 2r 2r 2r 2r 2r 2r 2r v -f refh v -f refl v out r fb v refh v -s refh v -s refl r fb (1) 5k w 5k w note: (1) r = 5k w for gain = 1 fb r = 10k w for g ia n = 2. fb
DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 figure 65. basic configuration copyright ? 2008, texas instruments incorporated submit documentation feedback 25 product folder link(s): DAC9881 load dac registers serial data in clock serial data out + 0.1 m f 1 m f +5v external reference +5.0000v 0v to +5.0v 1.8v to 5v reset dac registers sdosel chip-select sclk sdi ldac agnd av dd v -s refl (thermal pad) pdnrst usb/btc gainrstsel nc 12 3 4 5 6 1817 16 15 14 13 DAC9881 iov dd sdo dgnd av dd sdosel cs 24 23 22 21 20 19 v -s refh v out r f b v -f refl v -f refh nc 7 8 9 10 11 12 + 0.1 f m 1 f m
analog output DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com the DAC9881 offers a force and sense output configuration for the high open-loop gain output amplifier. this feature allows the loop around the output amplifier to be closed at the load (as shown in figure 66 ), thus ensuring an accurate output voltage. the output buffer v out and r fb pins are provided so that the output op amp buffer feedback can be connected at the load. without a driven load, the DAC9881 output typically swings to within 15mv of the agnd and av dd supply rails. because of the high accuracy of these dacs, system design problems such as grounding and wiring resistance become very important. a 18-bit converter with a 5v full-scale range has an lsb value of 19 m v. the DAC9881 has a typical feedback resistor current of 0.5ma; thus, a series wiring resistance of only 100m ? (r w1 ) causes a voltage drop of 50 m v. in terms of a system layout, the resistivity of a typical 1-ounce copper-clad printed circuit board (pcb) is 0.5m ? per square. for a 0.5ma current, a 0.25mm wide printed circuit conductor 25mm long results in a voltage drop of 25 m v. note that the wiring resistance of r w2 is not critical as long as the feedback resistor (r fb ) is connected at the driven load. figure 66. analog output closed-loop configuration (r w1 and r w2 represent wiring resistance) 26 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 load dac registers serial data in clock serial data out + 0.1 f m 1 f m +5v external reference +5.0000v v out 1.8v to 5v reset dac registers sdosel chip-select sclk sdi ldac agnd av dd v -s refl (thermal pad) pdnrst usb/btc gainrstsel nc 12 3 4 5 6 1817 16 15 14 13 DAC9881 iov dd sdo dgnd av dd sdosel cs 24 23 22 21 20 19 v -s refh v out r fb v -f ref l v -f refh nc r w2 r w1 7 8 9 10 11 12 + 0.1 f m 1 f m
reference inputs DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 the reference high input, v refh , can be set to any voltage in the range of 1.25v to av dd . the reference low input, v refl , can be set to any voltage in the range of ? 0.2v to +0.2v (to provide a small offset to the output of the DAC9881, if desired). the current into v refh and out of v refl depends on the dac code, and can vary from approximately 0.5ma to 1ma in the gain = 1x mode of operation. the reference high and low inputs appear as variable loads to the external reference circuit. if the external references can source or sink the required current, and if low impedance connections are made to the v refh and v refl pins, external reference buffers are not required. figure 65 shows a simple configuration of the DAC9881 using external references without force and sense reference buffers. kelvin sense connections for the reference high and low are included on the DAC9881. when properly used with external reference buffer op amps, these reference kelvin sense pins ensure that the driven reference high and low voltages remain stable versus varying reference load currents. figure 67 shows an example of a reference force and sense configuration of the DAC9881 operating from a single analog reference voltage. both the v refl and v refh reference voltages are set to levels of 100mv from the DAC9881 supply rails, and are derived from a +5v external reference. figure 68 illustrates the effect of not using the reference force and sense buffers to drive the DAC9881 v refl and v refh pins. figure 69 shows the improvement when using the reference buffers. a slight degradation in inl and dnl performance is seen without the use of the force and sense buffer configuration. figure 67. buffered references (v refh = +4.900v and v refl = 100mv). figure 68. linearity and differential linearity error figure 69. linearity and differential linearity error for figure 65 without reference buffers for figure 67 with reference buffers copyright ? 2008, texas instruments incorporated submit documentation feedback 27 product folder link(s): DAC9881 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 le (lsb) 0 32768 65536 98304 131072 digital input code 163840 196608 229376 262144 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dle (lsb) 2k w 96k w +5v external reference +5.0000v opa2350 2200pf2200pf 1000pf1000pf sclk sdi ldac agnd av dd v -s refl 12 3 4 5 6 DAC9881 v -s refh v out r fb v -f refl v f ref h- nc 7 8 9 10 11 12 2k w 50 w 50 w +4.900v+0.100v note: v can be connected to agnd if v is not biased. refl refl 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 le (lsb) 0 32768 65536 98304 131072 digital input code 163840 196608 229376 262144 2.01.5 1.0 0.5 0 - 0.5 - 1.0 - 1.5 - 2.0 dle (lsb)
output range (1) input data format power down hardware reset DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com the maximum output range of the DAC9881 is v refl to (v refh ? v refl ) g, where g is the output buffer gain set by the gain pin. when the gain pin is connected to dgnd, the output buffer gain = 1. when the gain pin is connected to iov dd , the output buffer gain = 2. the output range must not be greater than av dd ; otherwise, output saturation occurs. the DAC9881 output transfer function is given in equation 1 : where: code = 0 to 262143. this is the digital code loaded to the dac. buffer gain = 1 or 2 (set by the gain pin). v refh = reference high voltage applied to the device. v refl = reference low voltage applied to the device. the usb/ btc pin defines the input data format. when this pin is connected to iov dd , the input data format is straight binary, as shown in table 1 . when this pin is connected to dgnd, the input data format is twos complement, as shown in table 2 . table 1. output vs straight binary code usb code 5v range description 3ffffh +4.99998 +full-scale ? 1lsb 30000h +3.75000 3/4-scale 20000h +2.50000 midscale 10000h +1.25000 1/4-scale 00000h 0.00000 zero-scale table 2. output vs twos complement code btc code 5v range description 1ffffh +4.99998 +full-scale ? 1lsb 10000h +3.75000 3/4-scale 00000h +2.50000 midscale 3ffffh +2.49998 midscale ? 1lsb 30000h +1.25000 1/4-scale 20000h 0.00000 zero-scale the DAC9881 has a hardware power-down function. when the pdn pin is high, the device is in power-down mode. when the device is in power-down, the v out pin is connected to ground through an internal 10k ? resistor, but the contents of the input register and the dac latch do not change and spi communication remains active. when the pdn pin returns low, the device returns to normal operation. when the rst pin is low, the device is in hardware reset mode, and the input register and dac latch are set to the value defined by the rstsel pin. after rst goes high, the device is in normal operating mode, and the input register and dac latch maintain the reset value until new data are written. 28 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881 v v - refh refl 262144 code buffer gain + v refl v out =
power-on reset program reset value serial interface input shift register DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 the DAC9881 has a power-on reset function. after power-on, the value of the input register, the dac latch, and the output from the v out pin are set to the value defined by the rstsel pin. after a power-on reset or a hardware reset, the output voltage from the v out pin and the values of the input register and dac latch are determined by the status of the rstsel pin and the input data format, as shown in table 3 . table 3. reset value rstsel pin usb/ btc pin input format v out value of input register and dac latch dgnd iov dd straight binary 0 00000h iov dd iov dd straight binary midscale 20000h dgnd dgnd twos complement midscale 00000h iov dd dgnd twos complement 0 20000h the DAC9881 is controlled by a versatile three-wire serial interface that operates at clock rates of up to 50mhz and is compatible with spi, qspi?, microwire?, and dsp interface standards. data are loaded into the device as a 24-bit word under the control of the serial clock input, sclk. the timing diagrams for this operation are shown in the timing diagram section. the cs input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be transferred into the device only while cs is low. when cs is high, the sclk and sdi signals are blocked out, and sdo is in high-z status. to start the serial data transfer, cs should be taken low, observing the minimum delay from cs falling edge to sclk rising edge, t 2 . after cs goes low, serial input data from sdi are clocked into the device input shift register on the rising edges of sclk for 24 or more clock pulses. if a frame contains less than 24 bits of data, the frame is invalid. invalid input data are not written into the input register and dac, although the input register and dac will continue to hold data from the preceding valid data cycle. if more than 24 bits of data are transmitted in one frame, the last 24 bits are written into the shift register and dac. cs may be taken high after the rising edge of the 24th sclk pulse, observing the minimum sclk rising edge to cs rising edge time, t 7 . the contents of the shift register are transferred into the input register on the rising edge of cs. when data have been transferred into the input register of the dac, the corresponding dac register and dac output can be updated by taking the ldac pin low. table 4 shows the input shift register data word format. d17 is the msb of the 18-bit dac data. table 4. input shift register data word format b17 b0 bit b23 b22 b21 b20 b19 b18 (msb) b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 (lsb) data x (1) x x x x x d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (1) x = don ' t care. stand-alone mode when the sdosel pin is tied to iov dd , the interface is in stand-alone mode. this mode provides serial readback for diagnostic purposes. the new input data (24 bits) are clocked into the device shift register and the existing data in the input register (24 bits) are shifted out from the sdo pin. if more than 24 sclks are clocked when cs is low, the contents of the input register are shifted out from the sdo pin, followed by zeroes; the last 24 bits of input data remain in the shift register. if less than 24 sclks are clocked while cs is low, the data from the sdo pin are part of the data in the input register and must be ignored. refer to figure 2 for further details. daisy-chain mode when the sdosel pin is tied to gnd, the interface is in daisy-chain mode. for systems that contain several dacs, the sdo pin may be used to daisy-chain several devices together. copyright ? 2008, texas instruments incorporated submit documentation feedback 29 product folder link(s): DAC9881
double-buffered interface load dac pin ( ldac) 1.8v to 5v logic interface power-supply sequence DAC9881 sbas438a ? may 2008 ? revised august 2008 ......................................................................................................................................................... www.ti.com in daisy-chain mode, sclk is continuously applied to the input shift register while cs is low. if more than 24 clock pulses are applied, the data ripple out of the shift register and appear on the sdo line. these data are clocked out on the falling edge of sclk and are valid on the rising edge. by connecting this line to the sdi input on the next dac in the chain, a multi-dac interface is constructed. 24 clock pulses are required for each dac in the chain. therefore, the total number of clock cycles must be equal to (24 x n), where n is the total number of devices in the chain. when the serial transfer to all devices is complete, cs should be taken high. this action prevents any further data from being clocked into the input shift register. the contents in the shift registers are transferred into the relevant input registers on the rising edge of the cs signal. a continuous sclk source may be used if cs can be held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles can be used and cs can be taken high some time later. when the transfer to all input registers is complete, a common ldac signal updates all dac registers, and all analog outputs update simultaneously. the DAC9881 has a double-buffered interface consisting of two register banks: the input register and the dac latch. the input register is connected directly to the input shift register and the digital code is transferred to the input register upon completion of a valid write sequence. the dac latch contains the digital code used by the resistor r-2r ladder. the contents of the dac latch defines the output from the dac. access to the dac latch is controlled by the ldac pin. when ldac is high, the dac latch is latched and the input register can change state without affecting the contents of the dac latch. when ldac is low, however, the dac latch becomes transparent and the contents of the input register is transferred to the dac register. ldac transfers data from the input register to the dac latch (and, therefore, updates the dac output). the contents of the dac latch (and the output from dac) can be changed in two ways, depending on the status of ldac. synchronous mode when ldac is tied low, the dac latch updates as soon as new data are transferred into the input register after the rising edge of cs. asynchronous mode when ldac is high, the dac latch is latched. the dac latch (and dac output) is not updated at the same time that the input register is written to. when ldac goes low, the dac latch updates with the contents of the input register. all digital input and output pins are compatible with any logic supply voltage between 1.8v and 5v. connect the interface logic supply voltage to the iov dd pin. although timing is specified down to 2.7v (see the timing characteristics ), iov dd can operate as low as 1.8v, but with degraded timing and temperature performance. for the lowest power consumption, logic v ih levels should be as close as possible to iov dd , and logic v il levels should be as close as possible to gnd. for the device to work properly, iovdd must not come up before av dd , and the reference voltage must come up after the av dd supply. additionally, because the dac input shift register is not reset during a power-on reset or hardware reset, the cs pin must not be unintentionally asserted during power-up of the device. to avoid improper power-up, it is recommended that the cs and ldac pins be connected to iov dd through pull-up resistors. to ensure that the electrostatic discharge (esd) protection circuitry of this device is not activated, all other digital pins must be held at ground potential until iov dd is applied. 30 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): DAC9881
application information bipolar operation using the DAC9881 (2) (3) (4) DAC9881 www.ti.com ......................................................................................................................................................... sbas438a ? may 2008 ? revised august 2008 the DAC9881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit shown in figure 70 . this circuit gives a bipolar output voltage of v bip . when gain = 1, v bip can be calculated using equation 2 : where: v bip (code) = bipolar output voltage versus code from the opa211 . code = 0 to 262143. this is the digital code loaded to the dac. v ref = reference high voltage applied to the DAC9881. by first choosing a value for resistor r 3 , r 1 and r 2 can be determined by equation 3 and equation 4 , respectively: where: v bip = peak desired output voltage for bipolar output. v ref = reference high voltage applied to the DAC9881. note: v bip v ref . r 3 = opa211 feedback resistor chosen by user. note that r 2 is not required in the circuit of figure 70 for bipolar output voltage ranges equal to v ref . using the previous equations, and with v ref = 5v and r 3 set to 10k ? , a 8v output span can be achieved with r 1 calculated to be 6.25k ? and r 2 to be 16.67k ? . similarly, a near 15v rail-to-rail output can be achieved with r 1 calculated to be 3.33k ? and r 2 calculated to be 5k ? . figure 70. bipolar operation using the DAC9881 copyright ? 2008, texas instruments incorporated submit documentation feedback 31 product folder link(s): DAC9881 v bip (code) = 1 + r 3 r 1 v ref r 3 r 2 r 3 r 1 + code 262144 - r 3 r 1 = v ref v bip r 2 = v ref r 3 v bip v - ref DAC9881 r 1 r 2 v bip v refl v refh v ref r 3 opa211 v out +15v - 15v note: some pins omitted for clarity.
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) DAC9881sbrger active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year DAC9881sbrget active vqfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year DAC9881srger active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year DAC9881srget active vqfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 2-sep-2008 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DAC9881sbrger vqfn rge 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 DAC9881sbrget vqfn rge 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 DAC9881srger vqfn rge 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 DAC9881srget vqfn rge 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 package materials information www.ti.com 30-aug-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DAC9881sbrger vqfn rge 24 3000 340.5 333.0 20.6 DAC9881sbrget vqfn rge 24 250 340.5 333.0 20.6 DAC9881srger vqfn rge 24 3000 340.5 333.0 20.6 DAC9881srget vqfn rge 24 250 340.5 333.0 20.6 package materials information www.ti.com 30-aug-2008 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or "enhanced plastic." only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband clocks and timers www.ti.com/clocks digital control www.ti.com/digitalcontrol interface interface.ti.com medical www.ti.com/medical logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony rf/if and zigbee? solutions www.ti.com/lprf video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2008, texas instruments incorporated

▲Up To Search▲

Price & Availability of DAC9881

	To Download DAC9881 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .